電子及電氣技術(shù)-英譯中模板

1.? High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications

高性能汽車級(jí)微控制器，用于與安全密切相關(guān)的應(yīng)用
– Dual CPUs Running in Lockstep

運(yùn)行步伐一致的雙CPU
– ECC on Flash and RAM Interfaces

對(duì)閃存及隨機(jī)存儲(chǔ)器接口進(jìn)行錯(cuò)誤檢查及糾正

– Built-In Self-Test (BIST) for CPU and On-chip RAMs

內(nèi)置中央處理器及片上只讀存儲(chǔ)器自測(cè)功能（BIST）
– Error Signaling Module With Error Pin

帶有錯(cuò)誤引腳的錯(cuò)誤信號(hào)傳送模塊，

– Voltage and Clock Monitoring

電壓及時(shí)鐘監(jiān)控
? ARM® Cortex®-R4F 32-Bit RISC CPU

ARM® Cortex®-R4F，32位精簡(jiǎn)指令集中央處理器
– 1.66 DMIPS/MHz With 8-Stage Pipeline

運(yùn)算速度為166萬(wàn)條指令每秒/兆赫茲，8通道
– FPU With Single- and Double-Precision

浮點(diǎn)運(yùn)算單元，包含單精度和雙精度
– 12-Region Memory Protection Unit (MPU)

12個(gè)區(qū)域存儲(chǔ)器保護(hù)單元（MPU）
– Open Architecture With Third-Party Support

開(kāi)放的架構(gòu)，由第三方支持
? Operating Conditions

運(yùn)行條件
– Up to 180-MHz System Clock

系統(tǒng)時(shí)鐘頻率最高可達(dá)180兆赫茲
– Core Supply Voltage (VCC): 1.14 to 1.32 V

芯片供電電壓（VCC）為：1.14 到1.32 V
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

輸入/輸出供電電壓(VCCIO)為：3.0 到3.6 V
Packages

封裝

– 144-Pin Quad Flatpack (PGE) [Green]

四邊形平版封裝，144個(gè)引腳（PGE）[綠色]

– 337-Ball Grid Array (ZWT) [Green]

網(wǎng)格陣列封裝，337個(gè)球形引腳（ZWT）[綠色]

2.Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain the output voltage at or below VREFLOW.

當(dāng)輸出緩沖器將輸出驅(qū)動(dòng)到一個(gè)較低的電壓水平時(shí)，如果輸出電壓低于VREFLOW,那么輸出緩沖器的阻抗將增加到高阻狀態(tài)。在使用容性負(fù)載或者任何無(wú)電流流過(guò)（例如，當(dāng)一條接地電阻路徑的電壓被緩沖器驅(qū)動(dòng)為低水平時(shí)）的負(fù)載時(shí)，內(nèi)部接地母線與輸出引腳之間將發(fā)生高度解耦。緩沖器上用于拉高輸出電壓（使其高于 VREFLOW）的電流負(fù)載將與緩沖器的輸出阻抗成反比，可以確保輸出電壓小于或等于VREFLOW。